--- title: "VHDL Compiler - Reviews, Revenue and Downloads in United States | Apple App Store" description: "Write VHDL code directly on your iPhone, iPad and iPod Touch! This app is ideal for learning and testing code snippets! VHDL (VHSIC Hardware Description Language) is a hardware description language u" --- # VHDL Compiler — United States > Learn and code in VHDL ![VHDL Compiler App Icon](https://is1-ssl.mzstatic.com/image/thumb/Purple221/v4/c1/ec/a7/c1eca73d-b1ff-420a-8a3a-9ad5935aecf5/AppIcon-0-0-1x_U007emarketing-0-5-0-0-85-220.png/434x0w.png) **Developer:** [Ketan Appa](https://apptail.io/developer/ketan-appa-Zzb) (United Kingdom) **Category:** Education **Rating:** 2.7/5 (7 ratings) **Price:** Free **Bundle ID:** com.kappsmart.vhdlcompiler **Store:** Apple App Store **Country:** United States **Version:** 2.4 (released 2026-03-10) **Original Release:** 2019-04-28 **Languages:** English **App Store Link:** [Download on Apple App Store](https://apps.apple.com/us/app/app/id1459379888) **AppTail Page:** [https://apptail.io/app/vhdl-compiler-LVfc/united-states](https://apptail.io/app/vhdl-compiler-LVfc/united-states) ## VHDL Compiler Description Write VHDL code directly on your iPhone, iPad and iPod Touch! This app is ideal for learning and testing code snippets! VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language. This app uses the open-source GHDL simulator ( GHDL is a VHDL compiler that can execute (nearly) any VHDL program. GHDL is not a synthesis tool: you cannot create a netlist with GHDL (yet). Features: - Compile and run your program - View program output or detailed error - Custom keyboard for easy input of frequently used characters - Optimized for connecting with external physical/bluetooth keyboard - Advanced source code editor with syntax highlighting and line numbers - Open, save, import and share VHDL files. Limitations: - Internet connection is required for compilation - Maximum program running time is 20s - One file can be run at a time - All entities should be have the same name as their files. ## VHDL Compiler Screenshots - [Screenshot 1](https://is1-ssl.mzstatic.com/image/thumb/Purple126/v4/dc/bd/3b/dcbd3b21-430f-b3e1-2fe7-73f5bb20713f/pr_source.png/1242x2688.png) - [Screenshot 2](https://is1-ssl.mzstatic.com/image/thumb/Purple116/v4/46/26/72/46267237-0960-fdc1-2998-a4d81d6d12e1/pr_source.png/1242x2688.png) - [Screenshot 3](https://is1-ssl.mzstatic.com/image/thumb/Purple126/v4/72/4f/a9/724fa999-a439-6501-4dd9-fcba68cda6ba/pr_source.png/1242x2688.png) - [Screenshot 4](https://is1-ssl.mzstatic.com/image/thumb/PurpleSource116/v4/2a/9f/36/2a9f362e-38db-ed6a-2d28-bc9b7d4c9f04/018e840d-3ca8-448f-895f-9bd67c65e0b7_Simulator_Screenshot_-_iPhone_11_Pro_Max_-_2023-09-21_at_17.35.55.png/1242x2688.png) - [Screenshot 5](https://is1-ssl.mzstatic.com/image/thumb/PurpleSource116/v4/84/44/64/84446466-3c6d-bb3c-d740-9d9f4eb59d34/27d34d1f-dc7e-4f46-afd3-26e856d412ac_Simulator_Screenshot_-_iPhone_11_Pro_Max_-_2023-09-21_at_17.36.00.png/1242x2688.png) ## VHDL Compiler Rating Breakdown in United States - 5 stars: 2 (29%) - 4 stars: 1 (14%) - 3 stars: 0 (0%) - 2 stars: 1 (14%) - 1 stars: 3 (43%) ## VHDL Compiler Reviews in United States ### ***** "Works great simulates std_logic circuits just fine" I realized that it’s essential to limit simulation with ultimately a WAIT; statement including a clock generator with limited total time Here is a simple test setup beyond just text: Enjoy.. great job by the developer of the App and the original open source VHDL Compiler Designer ———————————————— -- Hello world program library IEEE; use IEEE.std_logic_1164.all; use std.textio.all; -- Imports the standard textio package. -- Defines a design entity, without any ports. entity hello is end hello; architecture behaviour of hello is signal index : integer:=0; signal clk : std_logic := '0'; begin process(clk) variable l : line; begin if(rising_edge(clk)) then write(l,String'("/")); writeline (output, l); end if; end process; process begin index <= index +1; clk <= not clk; wait for 1 ns; if index > 20 then wait; end if; end process; end behaviour; -- Tdurrer, 2019-11-08 [View all VHDL Compiler reviews and detailed analytics on AppTail](https://app.apptail.io/signup?utm_campaign=ai-crawl&utm_content=reviews) ## VHDL Compiler In-App Purchases | Item | Price | |------|-------| | Upgrade | $2.99 | ## Apps Similar to VHDL Compiler - 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